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cyrf6936 wirelessusb? lp 2.4 ghz radio soc cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-16015 rev. *j revised april 18, 2011 features 2.4 ghz direct sequence spread spectrum (dsss) radio transceiver operates in the unlicensed worldwide industrial, scientific, and medical (ism) band (2.400 ghz to 2.483 ghz) 21 ma operating current (transmit at ?5 dbm) transmit power up to +4 dbm receive sensitivity up to ?97 dbm sleep current less than 1 a dsss data rates up to 250 kbps, gfsk data rate of 1 mbps low external component count auto transaction sequencer (ats) - no mcu intervention framing, length, crc16, and auto ack power management unit (pmu) for mcu/sensor fast startup and fast channel changes separate 16-byte transmit and receive fifos autorate? - dynamic da ta rate reception receive signal strength indication (rssi) serial peripheral interface (spi) control while in sleep mode 4 mhz spi microcontroller interface battery voltage monitoring circuitry supports coin-cell operated applications operating voltage from 1.8 v to 3.6 v operating temperature from 0 to 70c space saving 40-pin qfn 6x6 mm package applications wireless keyboards and mice wireless gamepads remote controls to y s voip and wireless headsets white goods consumer electronics home automation automatic meter readers personal health and entertainment applications support see www.cypress.com for development tools, reference designs, and application notes. logic block diagram rf bias data interface and sequencer dsss baseband & framer spi synthesizer gfsk demodulator gfsk modulator irq ss sck miso mosi rf p rf n xtal xout rssi xtal osc power management l/d v dd v bat v reg rst gnd v cc pactl [+] feedback
cyrf6936 document #: 38-16015 rev. *j page 2 of 28 contents functional description ..................................................... 3 functional overview ........................................................ 4 data transmission modes ........................................... 4 link layer modes ........................................................ 4 packet buffers ............................................................. 5 auto transaction sequencer (ats) ............................ 5 data rates .................................................................. 6 functional block overview .............................................. 6 2.4 ghz radio ............................................................. 6 frequency synthesizer ................................................ 6 baseband and framer ................................................. 6 packet buffers and radio configuration registers ..... 6 spi interface ................................................................ 6 interrupts ..................................................................... 8 clocks ......... .............. .............. .............. .............. ......... 8 power management ............... .............. .............. ......... 8 low noise amplifier and received signal strength indication .... ........................................ 8 receive spurious response .. ..................................... 9 application examples ......................................................9 registers .........................................................................14 absolute maximum ratings ...........................................15 operating conditions .....................................................15 dc characteristics ..........................................................15 ac characteristics ..........................................................16 rf characteristics ..........................................................17 typical operating characteristics .................................19 ordering information ......................................................22 ordering code definitions ..... ....................................22 package description ............... .............. .............. ...........23 acronyms ........................................................................25 document conventions .................................................25 units of measure .......................................................25 document history page .................................................26 sales, solutions, and legal information ......................28 worldwide sales and design support ......... ..............28 products ....................................................................28 psoc solutions .........................................................28 [+] feedback
cyrf6936 document #: 38-16015 rev. *j page 3 of 28 functional description the cyrf6936 wirelessusb? lp radio is a second generation member of the cypress wirelessusb radio system-on-chip (soc) family. the cyrf6936 is interoperable with the firs t generation cywusb69xx devices. the cyrf6936 ic adds a range of enhanced features, including increased op erating voltage range, reduced supply curr ent in all operating modes, higher data rate options, reduced crystal start up, synthe sizer settling, and link turnaround times. figure 1. pin diagram - cyrf6936 40 qfn rf bias nc nc v bat2 v cc v bat1 xtal v cc nc nc v reg nc nc v bat0 l/d nc nc v i/o v dd rst rf n nc nc v cc nc nc resv nc gnd rf p nc ss sck irq / gpio mosi / sdat miso / gpio xout / gpio pactl / gpio nc nc * e-pad bottom side 21 22 23 24 25 26 27 28 29 30 11 12 13 14 15 16 17 18 19 20 10 9 8 7 6 5 4 3 2 40 39 38 37 36 35 34 33 32 31 1 cyrf6936 wirelessusb lp 40-pin qfn corner tabs table 1. pin description pin number name type default description 1 xtal i i 12 mhz crystal. 2, 4, 5, 9, 14, 15, 17, 18, 20, 21, 22, 23, 31, 32, 36, 39 nc nc connect to gnd. 3, 7, 16 v cc pwr v cc = 2.4 v to 3.6 v. typically connected to v reg. 6, 8, 38 v bat(0-2) pwr v bat = 1.8 v to 3.6 v. main supply. 10 rf bias o o rf i/o 1.8 v reference voltage. 11 rf p i/o i differential rf signal to and from antenna. 12 gnd gnd ground. 13 rf n i/o i differential rf signal to and from antenna. 19 resv i must be connected to gnd. 24 ss i i spi enable, active low assertion. enables and frames transfers. 25 sck i i spi clock. 26 irq i/o o interrupt output (configurable acti ve high or low), or gpio. 27 mosi i/o i spi data input pin (master out slave in), or sdat. 28 miso i/o z spi data output pin (master in slave out), or gpio (in spi 3-pin mode). tri-states when spi 3pin = 0 and ss is deasserted. 29 xout i/o o buffered 0.75, 1.5, 3, 6, or 12 mhz clock, pactl , or gpio. tri-states in sleep mode (configure as gpio drive low). 30 pactl i/o o control signal for external pa, t/r switch, or gpio. 33 v i/o pwr i/o interface voltage, 1.8?3.6 v. [+] feedback
cyrf6936 document #: 38-16015 rev. *j page 4 of 28 functional overview the cyrf6936 ic provides a complete wirelessusb spi to antenna wireless modems. the soc is designed to implement wireless device links operating in the worldwide 2.4 ghz ism frequency band. it is intended for systems compliant with worldwide regulations covered by etsi en 301 489-1 v1.41, etsi en 300 328-1 v1.3.1 (europe), fcc cfr 47 part 15 (usa and industry canada), and telec arib_t66_march, 2003 (japan). the soc contains a 2.4 ghz, 1 mbps gfsk radio transceiver, packet data buffering, packet framer, dsss baseband controller, received signal strength indication (rssi), and spi interface for data transfer and device configuration. the radio supports 98 discrete 1 mhz channels (regulations may limit the use of some of these channels in certain jurisdictions). the baseband performs dsss spreading/despreading, start of packet (sop), end of packet (eop) detection, and crc16 generation and checking. the baseband may also be configured to automatically transmit acknowledge (ack) handshake packets whenever a valid packet is received. when in receive mode, with packet framing enabled, the device is always ready to receive data transmitted at any of the supported bit rates. this ena bles the implementation of mixed-rate systems in which diff erent devices use different data rates. this also enables the im plementation of dynamic data rate systems that use high data rates at shorter distances or in a low-moderate interference environment or both. it changes to lower data rates at longer distances or in high interference environments or both. in addition, the cyrf6936 ic has a power management unit (pmu), which enables direct connection of the device to any battery voltage in the range 1.8 v to 3.6 v. the pmu conditions the battery voltage to provide th e supply voltages required by the device, and may supply external devices. data transmission modes the soc supports four different data transmission modes: in gfsk mode, data is transmitted at 1 mbps, without any dsss. in 8dr mode, eight bits are encoded in each derived code symbol transmitted. in ddr mode, two bits are encoded in each derived code symbol transmitted (as in the cywusb6934 ddr mode). in sdr mode, one bit is encoded in each derived code symbol transmitted (as in the cywusb6934 standard modes). both 64 chip and 32 chip pseudo noise (pn) codes are supported. the four data transmission modes apply to the data after the sop. in particular the length, data, and crc16 are all sent in the same mode. in general, lower data rates reduce packet error rate in any given environment. link layer modes the cyrf6936 ic device supports the following data packet framing features: sop packets begin with a two-symbol sop marker. this is required in gfsk and 8dr modes, but is op tional in ddr mode and is not supported in sdr mode. if framing is disabled then an sop event is inferred whenever two successive correlations are detected. the sop_code_adr code used for the sop is different from that used for the ? body? of the packet, and if desired may be a different length. sop must be configured to be the same length on both sides of the link. length there are two options for detecting the end of a packet. if sop is enabled, then the length field must be enabled. gfsk and 8dr must enable the length field. this is the first eight bits after the sop symbol, and is transmitted at the payload data rate. when the length field is enabled, an eop condition is inferred after reception of the number of bytes defined in the length field, plus two bytes for the crc16. the alternative to using the length 34 rst i i device reset. internal 10 kohm pull down resistor. active high, connect through a 0.47 f capacitor to v bat. must have rst = 1 event the first time power is applied to t he radio. otherwise the state of the radio control registers is unknown. 35 v dd pwr decoupling pin for 1.8 v logic r egulator, connect through a 0.47 f capacitor to gnd. 37 l/d o pmu inductor/diode connection, when used. if not used, connect to gnd. 40 v reg pwr pmu boosted output voltage feedback. e-pad gnd gnd must be soldered to ground. corner tabs nc nc do not solder the tabs and keep other signal traces clear. all tabs are common to the lead frame or paddle which is grounded after the pad is grounded. while they are visible to the user, they do not extend to the bottom. table 1. pin description (continued) pin number name type default description [+] feedback
cyrf6936 document #: 38-16015 rev. *j page 5 of 28 field is to infer an eop conditi on from a configurable number of successive noncorrelations; this option is not available in gfsk mode and is only recommended when using sdr mode. crc16 the device may be configured to append a 16 bit crc16 to each packet. the crc16 uses the usb crc polynomial with the added programmability of the s eed. if enabled, the receiver verifies the calculated crc16 for the payload data against the received value in the crc16 field. the seed value for the crc16 calculation is configurable, and the crc16 transmitted may be calculated using either the loaded seed value or a zero seed; the received data crc16 is checked against both the configured and zero crc16 seeds. crc16 detects the following errors: any one bit in error. any two bits in erro r (irrespective of how far apart, which column, and so on). any odd number of bits in error (irrespective of the location). an error burst as wide as the checksum itself. figure 2 shows an example packet with sop, crc16, and lengths fields enabled, and figure 3 shows a standard ack packet. figure 2. example packet format figure 3. exampl e ack packet format packet buffers all data transmission and reception use the 16 byte packet buffers - one for transmission and one for reception. the transmit buffer allows loading a complete packet of up to 16 bytes of payload data in one burst spi transaction. this is then transmitted with no further mcu in tervention. similarly, the receive buffer allows receiving an entire packet of payload data up to 16 bytes with no firmware intervention required until the packet reception is complete. the cyrf6936 ic supports packets up to 255 bytes. however, the actual maximum packet lengt h depends on the accuracy of the clock on each end of the link and the data mode. interrupts are provided to allow an mcu to use the transmit and receive buffers as fifos. when transmitting a packet longer than 16 bytes, the mcu can load 16 bytes initially, and add further bytes to the transmit buffer as tran smission of data creates space in the buffer. similarly, when receiving packets longer than 16 bytes, the mcu must fetch re ceived data from the fifo periodically during packet reception to prevent it from overflowing. auto transaction sequencer (ats) the cyrf6936 ic provides automated support for transmission and reception of acknowledged data packets. when transmitting in transaction mode, the device automatically: starts the crystal and synthesizer enters transmit mode transmits the packet in the transmit buffer transitions to receive mode and waits for an ack packet transitions to the transaction end state when an ack packet is received or a timeout period expires similarly, when receiving in transaction mode, the device automatically: waits in receive mode for a valid packet to be received transitions to transmit m ode, transmits an ack packet transitions to the transaction end state (receive mode to await the next packet, and so on.) the contents of the packet buffers are not affected by the transmission or reception of ack packets. p sop 1 sop 2 length crc 16 payload data preamble n x 16us 1st framing symbol* 2nd framing symbol* packet length 1 byte period *note:32 or 64us p sop 1 sop 2 crc 16 pream ble n x 16us 1st fram ing sym bol* 2nd fram ing sym bol* crc field from received packet. 2 byte periods *note:32 or 64us [+] feedback
cyrf6936 document #: 38-16015 rev. *j page 6 of 28 in each case, the entire packet transaction takes place without any need for mcu firmware action (as long as packets of 16 bytes or less are used). to transmit data, the mcu must load the data packet to be transmitted, set the length, and set the tx go bit. similarly, when receiving packets in transaction mode, firmware must retrieve the fully received packet in response to an interrupt request indicating reception of a packet. data rates the cyrf6936 ic supports the following data rates by combining the pn code lengths and data transmission modes described in the previous sections: 1000 kbps (gfsk) 250 kbps (32 chip 8dr) 125 kbps (64 chip 8dr) 62.5 kbps (32 chip ddr) 31.25 kbps (64 chip ddr) 15.625 kbps (64 chip sdr) functional block overview 2.4 ghz radio the radio transceiver is a dual co nversion low if architecture optimized for power, range, and robustness. the radio employs channel-matched filters to ac hieve high performance in the presence of interference. an in tegrated power amplifier (pa) provides up to +4 dbm transmit power, with an output power control range of 34 db in seven st eps. the supply current of the device is reduced as the rf output power is reduced. frequency synthesizer before transmission or reception may begin, the frequency synthesizer must settle. the settling time varies depending on channel; 25 fast channels are provided with a maximum settling time of 100 s. the ?fast channels? (less than 100 s settling time) are every third channel, starting at 0 up to and in cluding 72 (for example, 0, 3, 6, 9 ?. 69, 72). baseband and framer the baseband and framer blocks provide the dsss encoding and decoding, sop generation and reception, crc16 generation and checking, and eop detection and length field. packet buffers and radio configuration registers packet data and configuration registers are accessed through the spi interface. all configur ation registers are directly addressed through the address field in the spi packet (as in the cywusb6934). configuration regi sters allow configuration of dsss pn codes, data rate, operating mode, interrupt masks, interrupt status, and so on. spi interface the cyrf6936 ic has an spi interface supporting communication between an application mcu and one or more slave devices (including the cy rf6936). the spi interface supports single-byte and multi-byte serial transfers using either 4-pin or 3-pin interfacing. the spi communications interface consists of slave select (ss ), serial clock (sck), master out-slave in (mosi), master in-sla ve out (miso), or serial data (sdat). spi communication may be described as the following: command direction (bit 7) = ?1 ? enables spi write transaction. a ?0? enables spi read transactions. command increment (bit 6) = ?1? enables spi auto address increment. when set, the address field automatically increments at the end of each data byte in a burst access. otherwise the same address is accessed. six bits of address eight bits of data the device receives sck from an application mcu on the sck pin. data from the application mcu is shifted in on the mosi pin. data to the application mcu is shifted out on the miso pin. the active low slave select (ss ) pin must be asserted to initiate an spi transfer. the application mcu can initiate spi data transfers using a multi-byte transaction. the first byte is the command/address byte, and the following bytes are the data bytes shown in table 3 through figure 6 on page 7 . the spi communications interf ace has a burst mechanism, where the first byte can be followed by as many data bytes as required. a burst transaction is terminated by deasserting the slave select (ss = 1). the spi communications interface single read and burst read sequences are shown in figure 4 and figure 5 on page 7 , respectively. the spi communications interfac e single write and burst write sequences are shown in figure 6 and figure 7 on page 7 , respectively. this interface may be optionally operated in a 3-pin mode with the miso and mosi functions combined in a single bidirectional data pin (sdat). when using 3-pin mode, user firmware must ensure that the mosi pin on the mcu is in a high impedance state except when mosi is actively transmitting data. table 2. internal pa output power step table pa setting typical output power (dbm) 7+4 60 5?5 4?13 3?18 2?24 1?30 0?35 [+] feedback
cyrf6936 document #: 38-16015 rev. *j page 7 of 28 the device registers may be writte n to or read from one byte at a time, or several sequential register locations may be written or read in a single spi transaction using incrementing burst mode. in addition to single byte confi guration register s, the device includes register files. register files are fifos written to and read from using nonincrementing burst spi transactions. the irq pin function may be optionally multiplexed onto the mosi pin. when this option is enabled, the irq function is not available while the ss pin is low. when using this configuration, user firmware must ensure that the mosi pin on the mcu is in a high impedance state whenever the ss pin is high. the spi interface is not dependent on the internal 12 mhz clock. registers may therefore be read from or written to when the device is in sleep mode, and the 12 mhz oscillator disabled. the spi interface and the irq and rst pins have a separate voltage reference pin (v i/o ). this enables the device to interface directly to mcus operating at voltages below the cyrf6936 ic supply voltage. figure 4. spi single read sequence figure 5. spi incrementing burst read sequence figure 6. spi single write sequence figure 7. spi incrementing burst write sequence table 3. spi transaction format parameter byte 1 byte 1+n bit # 7 6 [5:0] [7:0] bit name dir inc address data dir 0 inca5a4a3a2a1a0 d7 d6 d5 d4 d3 d2 d1 d0 sck mosi ss miso cmd addr data to mcu dir 0 inca5a4a3a2a1a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 data to mcu 1 cmd addr data to mcu 1+n sck mosi ss miso dir 1 inca5a4a3a2a1a0 d7 d6 d5 d4 d3 d2 d1 d0 sck mosi ss miso cmd addr data from mcu dir 1 inca5a4a3a2a1a0 d7 d6 d5 d4 d3 d2 d1 d0 sck mosi ss miso cmd addr data from mcu 1 d7 d6 d5 d4 d3 d2 d1 d0 data from mcu 1+n [+] feedback
cyrf6936 document #: 38-16015 rev. *j page 8 of 28 interrupts the device provides an inte rrupt (irq) out put, which is configurable to indicate the occurrence of various different events. the irq pin may be programmed to be either active high or active low, and be either a cmos or open drain output. the available interrupts are described in the section registers on page 14 . the cyrf6936 ic features three sets of interrupts: transmit, receive, and system interrupts. these interrupts all share a single pin (irq), but can be independently enabled or disabled. the contents of the enable registers are preserved when switching between transmit and receive modes. if more than one interrupt is enabled at any time, it is necessary to read the relevant status r egister to determine which event caused the irq pin to assert. even when a given interrupt source is disabled, the status of the condition that would otherwise cause an interrupt can be determined by reading the appropriate status register. it is therefore po ssible to use the devices without the irq pin, by polling the status registers to wait for an event, rather than using the irq pin. clocks a 12 mhz crystal (30 ppm or better) is directly connected between xtal and gnd without the need for external capacitors. a digital clock out function is provided, with selectable output frequencies of 0.75 , 1.5, 3, 6, or 12 mhz. this output may be used to clock an external microcontroller (mcu) or asic. this output is enabled by default, but may be disabled. the requirements to directly connect the crystal to the xtal pin and gnd are: nominal frequency: 12 mhz operating mode: fundamental mode resonance mode: parallel resonant frequency stability: 30 ppm series resistance: < 60 ohms load capacitance: 10 pf drive level: 100 w power management the operating voltage of the device is 1.8 v to 3.6 v dc, which is applied to the v bat pin. the device can be shut down to a fully static sleep mode by writing to the frc end = 1 and end state = 000 bits in the xact_cfg_adr register over the spi interface. the device enters sleep mode within 35 s after the last sck positive edge at the end of this spi transaction. alternatively, the device may be configured to automatically enter sleep mode after completing the packet transmission or reception. when in sleep mode, the on-chip oscillator is stopped, but the spi interface remains functional. the device wakes from sleep mode automatically when the device is commanded to enter transmit or receive mode. when resuming from sleep mode, there is a short delay while the oscillator restarts. the device can be configured to assert the irq pin when the oscillator has stabilized. the output voltage (v reg ) of the power management unit (pmu) is configurable to severa l minimum values between 2.4 v and 2.7 v. v reg may be used to provide up to 15 ma (average load) to external devices. it is possible to disable the pmu and provide an externally regulated dc supply voltage to the device?s main supply in the range 2.4 v to 3.6 v. the pmu also provides a regulated 1.8 v supply to the logic. the pmu is designed to provide high boost efficiency (74?85% depending on input voltage, output voltage, and load) when using a schottky diode and power inductor, eliminating the need for an external boost converter in many systems where other components require a boosted voltage. however, reasonable efficiencies (69?82% depending on input voltage, output voltage, and load) may be achieved when using low cost components such as sot23 diodes and 0805 inductors. the current through the diode must stay within the linear operating range of the diode. for some loads the sot23 diode is sufficient, but with higher loads it is not and an ss12 diode must be used to stay within this linear range of operation. along with the diode, the inductor used must not saturate its core. in higher loads, a lower resistance/higher saturation coil such as the inductor from sumida must be used. the pmu also provides a configurable low battery detection function, which may be read over the spi interface. one of seven thresholds between 1.8 v and 2.7 v may be selected. the interrupt pin may be configured to assert when the voltage on the v bat pin falls below the configured threshold. lv irq is not a latched event. battery monitoring is disabled when the device is in sleep mode. low noise amplifier and received signal strength indication the gain of the receiver can be controlled directly by clearing the agc en bit and writing to the low noise amplifier (lna) bit of the rx_cfg_adr register. clearing the lna bit reduces the receiver gain approximately 20 db, allowing accurate reception of very strong received signals (for example, when operating a receiver very close to the transmitter). approximately 30 db of receiver attenuation can be ad ded by setting the attenuation (att) bit. this limits data reception to devices at very short ranges. disabling agc and enabling lna is recommended, unless receiving from a device using external pa. when the device is in receive mode the rssi_adr register returns the relative signal strength of the on-channel signal power. when receiving, the device automatically measures and stores the relative strength of the signal being received as a five bit value. an rssi reading is tak en automatically when the sop is detected. in addition, a new rssi reading is taken every time the previous reading is read from the rssi_adr register, allowing the background rf energy level on any given channel to be easily measured when rssi is read while no signal is being received. a new reading can occur as fast as once every 12 s. [+] feedback
cyrf6936 document #: 38-16015 rev. *j page 9 of 28 receive spurious response the transmitter may exhibit spurs around 50mhz offset at levels approximately 50db to 60db below the carrier power. receivers operating at the transm it spur frequency may receive the spur if the spur level power is greater than the receive sensitivity level. the workaround for this is to program an additional byte in the packet header which contains the transmitter channel number. after the packet is received, the channel number can be checked. if the channel number does not match the receive channel then the packet is rejected. application examples figure 8. recommended circuit for systems where vbat 2.4 v keyboard interface power supply sdata issp sclk "-" xres "+" bind serial debug header layout j3 and j2.1 in a 0.100" spacing configuration e-pad must be soldered to ground. radio decoupling caps rf vco and vco buffer filter the power supply decoupling shown for vbat0 is a recommended cost effective configuration: c6=no load r2= 1ohm c7=10uf ceramic. for this configuration, it is required that c18 be installed. an alternate decoupling configuration is the following: c6=47uf ceramic r2=0ohm c7=.047uf. for this configuration, it is not required to load c18. for reference design part numbers, please refer to the bill of materials file 121-26504_a.xls. a 2-pin jumper installed from j3.1 to j2.1 enables the radio to power the processor. jumper removal is required when programming u2 to disconnect the radio from the miniprog 5v source. r1 is a zero ohm resistor that should be installed for production units only, following programming. miso mosi p1_1 sck p1_0 miso nss irq mosi clkout rst sck col16 col10 col17 col9 col13 p1_0 col15 col18 col12 col11 col14 nss p1_1 col5 col3 col2 col8 col1 col6 col7 col4 row5 row4 row6 row2 row7 row1 row8 row3 col7 col11 row4 row2 col1 col3 col8 col10 col14 row8 row3 col2 col6 row6 row5 col18 row1 col13 col16 col9 row7 col5 col4 col12 col15 col17 irq sw1 pactl evcc vcc vbat vbat vcc vbat vbat vcc evcc sot23 d1 bat400d 2 1 ind0402 l2 1.8 nh u2 cy7c60123-pvxc 30 16 17 18 29 28 26 25 19 23 12 5 7 24 10 20 43 21 42 22 6 34 35 36 37 38 39 40 41 13 14 15 31 32 33 27 44 11 9 8 4 1 2 3 46 47 48 45 p1_4 / sclk p0_7 p0_6 / tio1 p0_5 / tio0 p1_3 / ssel p1_2 p1_1 p1_0 p0_4 / int2 p0_0 / clkin p2_3 vdd1 p4_0 vss1 p2_5 p0_3 / int1 p4_3 p0_2 / int0 p4_2 p0_1 / clkout p4_1 p3_0 p3_1 p3_2 p3_3 p3_4 p3_5 p3_6 p3_7 p2_2 p2_1 p2_0 p1_5 / smosi p1_6 / smiso p1_7 vdd2 vss2 p2_4 p2_6 p2_7 nc4 nc1 nc2 nc3 nc6 nc7 nc8 nc5 s1 sw pushbutton 1a 2a 1b 2b 0402 c5 0.47 ufd ind0603 l1 22 nh 0603 r1 no load j1 kb 26 pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 tv4 0402 c8 1 ufd 6.3v bh1 batt con 2xaa 1 2 3 pos neg1 neg2 0402 c11 0.047 ufd 0402 c17 0.47 ufd 0805 r2 1 1% l3 10 uh tv5 0805 c12 10 ufd 6.3v 0805 c7 10 ufd 6.3v 0402 c20 0.01 ufd 0402 c16 0.047 ufd j3 1 pin hdr 1 tv8 j2 5 pin hdr 1 2 3 4 5 j4 3 pin hdr 1 2 3 0402 r3 47 tp2 tp1 0402 c13 0.047 ufd u1 cyrf6936 36 4 8 19 16 20 2 25 27 26 29 34 28 3 7 5 13 6 37 1 24 39 40 41 35 9 14 10 11 12 15 17 18 21 30 22 33 23 31 32 38 nc15 nc2 vbat2 resv vcc3 nc9 nc1 sck mosi irq xout rst miso vcc1 vcc2 nc3 rfn vbat1 l/d xtal ss nc16 vreg e-pad vdd nc4 nc5 rfbias rfp gnd1 nc6 nc7 nc8 nc10 pactl nc11 vio nc12 nc13 nc14 vbat0 0402 c3 2.0 pfd 0402 c1 15 pfd + e c18 100 ufd 10v 0402 c15 0.047 ufd tv7 tv6 ant1 wiggle 63 1 2 0402 c4 1.5 pfd y1 12 mhz crystal tv2 1210 c6 no load 0402 c10 0.047 ufd tv1 tv3 0402 c19 0.01 ufd 0402 c9 0.047 ufd [+] feedback
cyrf6936 document #: 38-16015 rev. *j page 10 of 28 table 4. recommended bom for systems where vbat 2.4 v item qty cy part number reference description manufacturer mfr part number 1 1 na ant1 2.5ghz h-stub wiggle antenna for 63mil pcb na na 2 1 na bh1 battery clips 2aa cell 3 1 730-10012 c1 cap 15pf 50 v ceramic npo 0402 panasonic ecj-0ec1h150j 4 1 730-11955 c3 cap 2.0 pf 50 v ceramic npo 0402 kemet c0402c209c5gactu 5 1 730-11398 c4 cap 1.5pf 50 v ceramic npo 0402 smd panasonic ecj-0ec1h1r5c 6 2 730r-13322 c5,c17 cap cer .47uf 6.3 v x5r 0402 murata grm155r60j474ke19d 7 2 730-13037 c12,c7 cap ceramic 10uf 6.3 v x5r 0805 kemet c0805c106k9pactu 8 1 730-13400 c8 cap 1 uf 6.3 v ceramic x5r 0402 panasonic ecj-0eb0j105m 9 6 730-13404 c9,c10,c11, c13,c15,c16 cap 0.047 uf 16 v ceramic x5r 0402 avx 0402yd473kat2a 10 1 710-13201 c18 cap 100uf 10 v elect fc panasonic - ecg eeu-fc1a101s 11 2 730-10794 c20,c19 cap 10000pf 16 v ceramic 0402 smd panasonic - ecg ecj-0eb1c103k 12 1 800-13317 d1 diode schottky 0.5a 40 v sot23 diodes inc bat400d-7-f 13 1 na j1 pcb copper pads none 14 1 420-11496 j2 conn hdr brkway 5pos str au pcb amp division of tyco 103185-5 15 1 420-11964 j3 header 1 pos 0.230 ht modii .100cl amp/tyco 103185-1 16 1 800-13401 l1 inductor 22nh 2% fixed 0603 smd panasonic - ecg elj-re22ngf2 17 1 800-11651 l2 inductor 1.8nh +-.3nh fixed 0402 smd panasonic - ecg elj-rf1n8df 18 1 800-10594 l3 coil 10uh 1100ma choke 0805 newark 30k5421 19 1 630-11356 r2 res 1.00 ohm 1/8w 1% 0805 smd yageo 9c08052a1r00fkhft 20 1 610-13402 r3 res 47 ohm 1/16w 5% 0402 smd panasonic - ecg erj-2gej470x 21 1 800-13368 s1 lt switch 6mm 100gf h=7mm th panasonic - ecg evq-pac07k 22 1 cyrf6936-40lf c u1 ic, lp 2.4 ghz radio soc qfn-40 cypress semiconductor cyrf6936 rev a5 23 1 cy7c60123-pv xc u2 ic wireless encore ii controller ssop48 cypress semiconductor cy7c60123-pvxc 24 1 800-13259 y1 crystal 12.00mhz hc49 smd ecera gf-1200008 25 1 pdc-9265-*b pcb printed circuit board cypress semiconductor pdc-9265-*b 26 1 920-11206 label1 serial number 27 1 920-26504 *a label 2 pca # 121-26504 *a [+] feedback
cyrf6936 document #: 38-16015 rev. *j page 11 of 28 no load components - do not install 28 1 730-13403 c6 cap 47uf 6.3 v ceramic x5r 1210 panasonic ecj-4yb0j476m 29 1 630-10242 r2 res chip 0.0 ohm 1/10w 5% 0805 smd phycomp usa inc 9c08052a0r00jlhft 30 1 730-13404 c7 cap 0.047 uf 50 v ceramic x5r 0402 avx 0402yd473kat2a 31 1 420-10921 j4 header 3pos fric strght mta 100 amp/tyco 644456-3 32 1 620-10519 r1 res zero ohm 1/16w 5% 0603 smd panasonic - ecg erj-3gey0r00v table 4. recommended bom for systems where vbat 2.4 v (continued) item qty cy part number reference description manufacturer mfr part number [+] feedback
cyrf6936 document #: 38-16015 rev. *j page 12 of 28 figure 9. recommended circuit for systems where v bat is 2.4 v - 3.6 v (pmu disabled) dp sw1 vbus dm nss sck miso mosi irq sw1 nled1 nled2 rst nled1 nled2 irq rst mosi sck nss miso 5v 5v vcc vcc 5v vcc vcc 5v vcc "bind" power supply "connect/activity" e-pad must be soldered to ground. u1 cyrf6936 u1 cyrf6936 nc15 36 nc2 4 vbat2 8 resv 19 vcc3 16 nc9 20 nc1 2 sck 25 mosi 27 irq 26 xout 29 rst 34 miso 28 vcc1 3 vcc2 7 nc3 5 rfn 13 vbat1 6 l/d 37 xtal 1 ss 24 nc16 39 vreg 40 e-pad 41 vdd 35 nc4 9 nc5 14 rfbias 10 rfp 11 gnd1 12 nc6 15 nc7 17 nc8 18 nc10 21 pactl 30 nc11 22 vio 33 nc12 23 nc13 31 nc14 32 vbat0 38 ind0402 l2 1.8 nh ind0402 l2 1.8 nh 0402 c9 0.047 ufd 0402 c9 0.047 ufd j1 usb a smt plug j1 usb a smt plug vbus 1 dm 2 dp 3 gnd 4 s1 5 s2 6 0402 c1 15 pfd 0402 c1 15 pfd d1 led green red d1 led green red gr 1 rd 2 c 3 c 4 0402 r1 zero 0402 r1 zero 0402 r2 620 0402 r2 620 ant1 wiggle 32 ant1 wiggle 32 1 2 0402 c12 1500 pfd 0402 c12 1500 pfd 0402 c10 0.047 ufd 0402 c10 0.047 ufd 0402 c3 2.0 pfd 0402 c3 2.0 pfd 0402 c7 0.047 ufd 0402 c7 0.047 ufd 0805 c13 4.7 ufd 0805 c13 4.7 ufd 0805 c14 2.2 ufd 0805 c14 2.2 ufd s1 sw ra push s1 sw ra push 1a 1b 2a 2b 0402 c6 0.047 ufd 0402 c6 0.047 ufd y1 12 mhz crystal y1 12 mhz crystal tv1 tv-20r tv1 tv-20r 0402 c15 0.47 ufd 0402 c15 0.47 ufd 0402 c11 0.047 ufd 0402 c11 0.047 ufd 0402 c4 1.5 pfd 0402 c4 1.5 pfd 0402 c8 0.047 ufd 0402 c8 0.047 ufd u2 cy7c63803-sxc u2 cy7c63803-sxc p0_0 7 p0_1 6 p0_2/int0 5 p0_3/int1 4 p0_4/int2 3 p0_5/tio0 2 p0_6/tio1 1 miso/p1_6 16 mosi/p1_5 15 vss 8 vcc 11 vreg 12 dm/p1_1 10 dp/p1_0 9 ssel/p1_3 13 sclk/p1_4 14 0402 c5 0.47 ufd 0402 c5 0.47 ufd ind0603 l1 22 nh ind0603 l1 22 nh [+] feedback
cyrf6936 document #: 38-16015 rev. *j page 13 of 28 table 5. recommended bom for systems where v bat is 2.4 v - 3.6 v (pmu disabled) item qty cy part number reference description manufacturer mfr part number 1 1 na ant1 2.5ghz h-stub wiggle antenna for 32mil pcb na na 2 1 730-10012 c1 cap 15pf 50 v ceramic npo 0402 panasonic ecj-0ec1h150j 3 1 730-11955 c3 cap 2.0 pf 50 v ceramic npo 0402 kemet c0402c209c5gactu 4 1 730-11398 c4 cap 1.5pf 50 v ceramic npo 0402 smd panasonic ecj-0ec1h1r5c 5 1 730-13322 c5, c15 cap 0.47 uf 6.3 v cera mic x5r 0402 murata grm155r60j474ke19d 6 7 6 730-13404 c6,c7,c8,c 9,c10,c11 cap 0.047 uf 16 v ceramic x5r 0402 avx 0402yd473kat2a 8 1 730-11953 c12 cap 1500pf 50 v ceramic x7r 0402 kemet c0402c152k5ractu 9 1 730-13040 c13 cap ceramic 4.7uf 6.3 v xr5 0805 kemet c0805c475k9pactu 10 1 730-12003 c14 cap cer 2.2uf 10 v 10% x7r 0805 murata electronics north america grm21br71a225ka01l 11 1 800-13333 d1 led green/red bicolor 1210 smd liteon ltst-c155kgjrkt 12 1 420-13046 j1 conn usb plug type a pcb smt acon uar72-4n5j10 13 1 800-13401 l1 inductor 22nh 2% fixed 0603 smd panasonic - ecg elj-re22ngf2 14 1 800-11651 l2 inductor 1.8nh +-.3nh fixed 0402 smd panasonic - ecg elj-rf1n8df 15 1 610-10343 r1 res zero ohm 1/16w 0402 smd panasonic - ecg erj-2ge0r00x 16 1 610-13472 r2 res chip 620 ohm 1/16w 5% 0402 smd panasonic - ecg erj-2gej621x 17 1 200-13471 s1 switch lt 3.5mmx2.9mm 160gf smd panasonic - ecg evq-p7j01k 18 1 cyrf6936-40lfc u1 ic, lp 2.4 ghz radio soc qfn-40 cypress semiconductor cyrf6936 rev a5 19 1 cy7c63803-sxc u2 ic low speed usb encore ii controller soic16 cypress semiconductor cy7c63803-sxc 20 1 800-13259 y1 crystal 12.00mhz hc49 smd ecera gf-1200008 21 1 pdc-9263-*b pcb printed circuit board cypress semiconductor pdc-9263-*b 22 1 label1 serial number xxxxxx 23 1 label2 pca # 121-26305 ** [+] feedback
cyrf6936 document #: 38-16015 rev. *j page 14 of 28 registers all registers are read and writable, except where noted. registers may be written to or read from individually or in sequential groups. [1, 2] table 6. register map summary address mnemonic b7 b6 b5 b4 b3 b2 b1 b0 default [1] access [1] 0x00 channel_adr not used channel -1001000 -bbbbbbb 0x01 tx_length_adr tx length 00000000 bbbbbbbb 0x02 tx_ctrl_adr tx go tx clr txb15 irqen txb8 irqen txb0 irqen txberr irqen txc irqen txe irqen 00000011 bbbbbbbb 0x03 tx_cfg_adr not used not used data code length data mode pa setting --000101 --bbbbbb 0x04 tx_irq_status_adr os irq lv irq txb15 irq txb8 irq txb0 irq txberr irq txc irq txe irq -------- rrrrrrrr 0x05 rx_ctrl_adr rx go rsvd rxb16 irqen rxb8 irqen rxb1 irqen rxberr irqen rxc irqen rxe irqen 00000111 bbbbbbbb 0x06 rx_cfg_adr agc en lna att hilo fast turn en not used rxow en vld en 10010-10 bbbbb-bb 0x07 rx_irq_status_adr rxow irq sopdet irq rxb16 irq rxb8 irq rxb1 irq rxberr irq rxc irq rxe irq -------- brrrrrrr 0x08 rx_status_adr rx ack pkt err eop err crc0 bad crc rx code rx data mode -------- rrrrrrrr 0x09 rx_count_adr rx count 00000000 rrrrrrrr 0x0a rx_length_adr rx length 00000000 rrrrrrrr 0x0b [1] pwr_ctrl_adr pmu en lvirq en pmu mode force pfet disable [3] lvi th pmu outv 10100000 bbbbbbbb 0x0c xtal_ctrl_adr xout fn xsirq en not used not used freq 000--100 bbb--bbb 0x0d io_cfg_adr irq od irq pol miso od xout od pactl od pactl gpio spi 3pin irq gpio 00000000 bbbbbbbb 0x0e gpio_ctrl_adr xout op miso op pactl op irq op xout ip miso ip pactl ip irq ip 0000---- bbbbrrrr 0x0f xact_cfg_adr ack en not used frc end end state ack to 1-000000 b-bbbbbb 0x10 framing_cfg_adr sop en sop len len en sop th 10100101 bbbbbbbb 0x11 data32_thold_adr not used not used not used not used th32 ----0100 ----bbbb 0x12 data64_thold_adr not used not used not used th64 ---01010 ---bbbbb 0x13 rssi_adr sop not used lna rssi 0-100000 r-rrrrrr 0x14 eop_ctrl_adr [4] hen hint eop 10100100 bbbbbbbb 0x15 crc_seed_lsb_adr crc seed lsb 00000000 bbbbbbbb 0x16 crc_seed_msb_adr crc seed msb 00000000 bbbbbbbb 0x17 tx_crc_lsb_adr crc lsb -------- rrrrrrrr 0x18 tx_crc_msb_adr crc msb -------- rrrrrrrr 0x19 rx_crc_lsb_adr crc lsb 11111111 rrrrrrrr 0x1a rx_crc_msb_adr crc msb 11111111 rrrrrrrr 0x1b tx_offset_lsb_adr strim lsb 00000000 bbbbbbbb 0x1c tx_offset_msb_adr not used not used not used not used strim msb ----0000 ----bbbb 0x1d mode_override_adr rsvd rsvd frc sen frc awake not used not used rst 00000--0 wwwww--w 0x1e rx_override_adr ack rx rxtx dly man rxack frc rxdr dis crc0 dis rxcrc ace not used 0000000- bbbbbbb- 0x1f tx_override_adr ack tx frc pre rsvd man txack ovrd ack dis txcrc rsvd tx inv 00000000 bbbbbbbb 0x26 xtal_cfg_adr rsvd rsvd rsvd rsvd start dly rsvd rsvd rsvd 00000000 wwwwwwww 0x27 clk_override_adr rsvd rsvd rsvd rsvd rsvd rsvd rxf rsvd 00000000 wwwwwwww 0x28 clk_en_adr rsvd rsvd rsvd rsvd rsvd rsvd rxf rsvd 00000000 wwwwwwww 0x29 rx_abort_adr rsvd rsvd abort en rsvd rsvd rsvd rsvd rsvd 00000000 wwwwwwww 0x32 auto_cal_time_adr auto_cal_time 00000011 wwwwwwww 0x35 auto_cal_offset_adr auto_cal_offset 00000000 wwwwwwww 0x39 analog_ctrl_adr rsvd rsvd rsvd rsvd rsvd rsvd rx inv all slow 00000000 wwwwwwww register files 0x20 tx_buffer_adr tx buffer file -------- wwwwwwww 0x21 rx_buffer_adr rx buffer file -------- rrrrrrrr 0x22 sop_code_adr sop code file note 5 bbbbbbbb 0x23 data_code_adr data code file note 6 bbbbbbbb 0x24 preamble_adr preamble file note 7 bbbbbbbb 0x25 mfg_id_adr mfg id file na rrrrrrrr notes 1. b = read/write; r = read only; w = write only; ?-? = not used, default value is undefined. 2. registers must be configured or accessed only when the radio is in idle or sleep mode. the pmu, gpios, and rssi registers can be accessed in active tx and rx mode. 3. pfet bit: setting this bit to "1" disabl es the fet, therefore safely allowing vbat to be connected to a separate reference fr om vcc when the pmu is disabled to the radio. 4. eop_ctrl_adr[6:4] must never have the value of ?000? , that is, eop hint symbol count must never be ?0? 5. sop_code_adr default = 0x17ff9e213690c782. 6. data_code_adr default = 0x02f9939702fa5ce3012bf1db0132be6f. 7. preamble_adr default = 0x333302. the count value must be great than 4 for ddr and greater than 8 for sdr. [+] feedback
cyrf6936 document #: 38-16015 rev. *j page 15 of 28 absolute maximum ratings exceeding maximum ratings may s horten the useful life of the device. user guidelines are not tested. storage temperature ................. .............. ... ?65c to +150c ambient temperature with powe r applied.. ?55c to +125c supply voltage on any power supply pin relative to v ss ...............................................?0.3 v to +3.9 v dc voltage to logic inputs [8] .................?0.3 v to v i/o +0.3 v dc voltage applied to outputs in high-z state.......................................?0.3 v to v i/o +0.3 v static discharge voltage (digital) [9] .......................... >2000 v static discharge voltage (rf) [9] ................................ 1100 v latch up current .....................................+200 ma, ?200 ma operating conditions v cc ...................................................................2.4 v to 3.6 v v i/o ...................................................................1.8 v to 3.6 v v bat ..................................................................1.8 v to 3.6 v t a (ambient temperature under bias) ............. 0c to +70c ground voltage................................................................. 0 v f osc (crystal frequency)........................... 12 mhz 30 ppm notes 8. it is permissible to connect voltages above v i/o to inputs through a series resistor limiting input current to 1 ma. ac timing not guaranteed. 9. human body model (hbm). 10. v reg depends on battery input voltage. 11. in sleep mode, the i/o interface voltage reference is v bat . 12. in sleep mode, v cc min. can be as low as 1.8 v. 13. includes current drawn while starting crystal, starting synthesizer, transmitting packet (including sop and crc16), changing to receive mode, and receiving ack handshake. device is in sleep e xcept during this transaction. 14. isb is not guaranteed if any i/o pi n is connected to voltages higher than v i/o . 15. i load_ext is dependent on external components and this entry applies when the components connected to l/d are ss12 series diode and dh53 100lc inductor from sumida. dc characteristics (t = 25 c, v bat = 2.4 v, pmu disabled, f osc = 12.000000 mhz) parameter description conditions min typ max unit v bat battery voltage 0?70 c1.83.6v v reg [10] pmu output voltage 2.4 v mode 2.4 2.43 v v reg [10] pmu output voltage 2.7 v mode 2.7 2.73 v v i/o [11] v i/o voltage 1.8 3.6 v v cc v cc voltage 0?70 c2.4 [12] 3.6 v v oh1 output high voltage condition 1 at i oh = ?100.0 a v i/o ? 0.2 v i/o v v oh2 output high voltage condition 2 at i oh = ?2.0 ma v i/o ? 0.4 v i/o v v ol output low voltage at i ol = 2.0 ma 0 0.45 v v ih input high voltage 0.7 v i/o v i/o v v il input low voltage 00.3 v i/o v i il input leakage current 0 < v in < v i/o ?1 0.26 +1 a c in pin input capacitance except xtal, rf n , rf p , rf bias 3.5 10 pf i cc (gfsk) [13] average tx i cc , 1 mbps, slow channel pa = 5, 2 way, 4 bytes/10 ms 0.87 ma i cc (32-8dr) [13] average tx i cc , 250 kbps, fast channel pa = 5, 2 way, 4 bytes/10 ms 1.2 ma i sb [14] sleep mode i cc 0.8 10 a i sb [14] sleep mode i cc pmu enabled 31.4 a idle i cc radio off, xtal active xout disabled 1.0 ma i synth i cc during synth start 8.4 ma tx i cc i cc during transmit pa = 5 (?5 dbm) 20.8 ma tx i cc i cc during transmit pa = 6 (0 dbm) 26.2 ma tx i cc i cc during transmit pa = 7 (+4 dbm) 34.1 ma rx i cc i cc during receive lna off, att on 18.4 ma rx i cc i cc during receive lna on, att off 21.2 ma boost eff pmu boost converter efficiency v bat = 2.5 v, v reg = 2.73 v, i load = 20 ma 81 % i load_ext [15] average pmu external load current v bat = 1.8 v, v reg = 2.73 v, 0?50 c, rx mode 15 ma i load_ext [15] average pmu external load current v bat = 1.8 v, v reg = 2.73 v, 50?70 c, rx mode 10 ma [+] feedback
cyrf6936 document #: 38-16015 rev. *j page 16 of 28 figure 10. spi timing ac characteristics [16] table 7. spi interface [17] parameter description min typ max unit t sck_cyc spi clock period 238.1 ns t sck_hi spi clock high time 100 ns t sck_lo spi clock low time 100 ns t dat_su spi input data setup time 25 ns t dat_hld spi input data hold time 10 ns t dat_val spi output data valid time 0 50 ns t dat_val_tri spi output data tri-state (mosi from slave select deassert) 20 ns t ss_su spi slave select setup time befor e first positive edge of sck [18] 10 ns t ss_hld spi slave select hold time afte r last negative edge of sck 10 ns t ss_pw spi slave select minimum pulse width 20 ns t sck_su spi slave select setup time 10 ns t sck_hld spi sck hold time 10 ns t reset minimum rst pin pulse width 10 ns sck nss mosi input mi so mosi output t sck_hi t sck_lo t ss_su t sck_su t sck_cyc t ss_hld t sck_hld t dat_su t dat_hld t dat_val t dat_val_tri notes 16. ac values are not guaranteed if voltage on any pin exceeding v i/o . 17. c load = 30 pf 18. sck must start low at the time ss goes low, otherwise the success of spi transactions are not guaranteed. [+] feedback
cyrf6936 document #: 38-16015 rev. *j page 17 of 28 rf characteristics notes 19. subject to regulation. 20. rssi value is not guaranteed. ext ensive variation from part to part. 21. exceptions f/3 & 5c/3. table 8. radio parameters parameter description conditions min typ max unit rf frequency range note 19 2.400 2.497 ghz receiver (t = 25c, v cc = v bat = 3.0 v, f osc = 12.000000 mhz, ber < 1e-3) sensitivity 125 kbps 64-8dr ber 1e-3 ?97 dbm sensitivity 250 kbps 32-8dr ber 1e-3 ?93 dbm sensitivity cer 1e-3 ?80 ?87 dbm sensitivity gfsk ber 1e-3, all slow = 1 ?84 dbm lna gain 22.8 db att gain ?31.7 db maximum received signal lna on ?15 ?6 dbm rssi value for pwr in ?60 dbm [20] lna on 21 count rssi slope 1.9 db/count interference performance (cer 1e-3) co-channel interference rejection carrier-to-interf erence (c/i) c = ?60 dbm 9 db adjacent (1 mhz) channel selectivity c/i 1 mhz c = ?60 dbm 3 db adjacent (2 mhz) channel selectivity c/i 2 mhz c = ?60 dbm ?30 db adjacent (> 3 mhz) channel selectivity c/i > 3 mhz c = ?67 dbm ?38 db out-of-band blocking 30 mhz?12.75 mhz [21] c = ?67 dbm ?30 dbm intermodulation c = ?64 dbm, f = 5,10 mhz ?36 dbm receive spurious emission 800 mhz 100 khz resbw ?79 dbm 1.6 ghz 100 khz resbw ?71 dbm 3.2 ghz 100 khz resbw ?65 dbm transmitter (t = 25c, v cc = 3.0 v) maximum rf transmit power pa = 7 +2 4 +6 dbm maximum rf transmit power pa = 6 ?2 0 +2 dbm maximum rf transmit power pa = 5 ?7 ?5 ?3 dbm maximum rf transmit power pa = 0 ?35 dbm rf power control range 39 db rf power range control step size seven steps, monotonic 5.6 db frequency deviation min pn code pattern 10101010 270 khz frequency deviation max pn code pattern 11110000 323 khz error vector magnitude (fsk error) >0 dbm 10 %rms occupied bandwidth ?6 dbc, 100 khz resbw 500 876 khz transmit spurious emission (pa = 7) in-band spurious second channel power (2 mhz) ?38 dbm in-band spurious third channel power (> 3 mhz) ?44 dbm [+] feedback
cyrf6936 document #: 38-16015 rev. *j page 18 of 28 non-harmonically related spurs (800 mhz) ?38 dbm non-harmonically related spurs (1.6 ghz) ?34 dbm non-harmonically related spurs (3.2 ghz) ?47 dbm harmonic spurs (second harmonic) ?43 dbm harmonic spurs (third harmonic) ?48 dbm fourth and greater harmonics ?59 dbm power management (crystal pn# ecera gf-1200008) crystal start to 10ppm 0.7 1.3 ms crystal start to irq xsirq en = 1 0.6 ms synth settle slow channels 270 s synth settle medium channels 180 s synth settle fast channels 100 s link turnaround time gfsk 30 s link turnaround time 250 kbps 62 s link turnaround time 125 kbps 94 s link turnaround time <125 kbps 31 s max packet length <60 ppm crystal-to-crystal all modes except 64-ddr and 64-sdr 40 bytes max packet length <60 ppm crystal-to-crystal 64-ddr and 64-sdr 16 bytes table 8. radio parameters (continued) parameter description conditions min typ max unit [+] feedback
cyrf6936 document #: 38-16015 rev. *j page 19 of 28 typical operating characteristics [22] receiver sensitivity vs. frequency offset -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -150 -100 -50 0 50 100 150 crystal offset (ppm) receiver sensitivity (dbm) rx sensitivity vs. vcc (1mbps cer) -94 -92 -90 -88 -86 -84 -82 -80 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc receiver sensitivity (dbm) transmit power vs. vcc (pmu off) -14 -12 -10 -8 -6 -4 -2 0 2 4 6 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc output power (dbm) transmit power vs. temperature (vcc = 2.7v) -14 -12 -10 -8 -6 -4 -2 0 2 4 6 0204060 temp (deg c) output power (dbm) receiver sensitivity vs channel (3.0v, room temp) -95 -93 -91 -89 -87 -85 -83 -81 020406080 channel receiver sensitivity (dbm) carrier to interferer (narrow band, lp modulation) -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 10.0 20.0 -10 -5 0 5 10 channel offset (mhz) c/i (db) rssi vs. channel (rx signal = -70dbm) 0 2 4 6 8 10 12 14 16 18 0 20406080 channel rssi count typical rssi count vs input power 0 8 16 24 32 -120 -100 -80 -60 -40 -20 input power (dbm) rssi count transmit power vs. channel -14 -12 -10 -8 -6 -4 -2 0 2 4 6 0 20406080 channel output power (dbm) average rssi vs. temperature (rx signal = -70dbm) 12 13 14 15 16 17 18 19 0204060 temp (deg c) rssi count pa7 pa6 pa5 pa4 pa7 pa6 pa5 pa4 pa7 pa6 pa5 pa4 lna on lna off lna off att on gfsk ddr32 8dr64 gfsk cer ddr32 8dr32 cer 8dr32 rx sensitivity vs. temperature (1mbps cer) -94 -92 -90 -88 -86 -84 -82 -80 0204060 temp (deg c) receiver sensitivity (dbm) cer 8dr32 average rssi vs. vcc (rx signal = -70dbm) 10 11 12 13 14 15 16 17 18 19 20 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc rssi count note 22. with lna on, att off, above -2dbm erroneous rssi values may be read. cross-checking rssi with lna off/on is recommended for accurate readings. [+] feedback
cyrf6936 document #: 38-16015 rev. *j page 20 of 28 typical operating characteristics (continued) gfsk vs. ber (sop threshold = 5, c38 slow) 0.00001 0.0001 0.001 0.01 0.1 1 10 100 -100 -80 -60 -40 -20 0 input power (dbm) %ber icc rx synth 7.8 7.9 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 9 9.1 9.2 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 temperature (c) operating current (ma) icc tx synth 7.8 7.9 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 9 9.1 9.2 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 temperature (c) operating current (ma) icc tx @ pa0 14 14.5 15 15.5 16 16.5 17 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 temperature (c) operating current (ma) icc tx @ pa1 14 14.5 15 15.5 16 16.5 17 17.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 temperature (c) operating current (ma) icc tx @ pa2 15 15.5 16 16.5 17 17.5 18 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 temperature (c) operating current (ma) icc tx @ pa3 15.5 16 16.5 17 17.5 18 18.5 19 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 temperature (c) operating current (ma) icc tx @ pa4 16.5 17 17.5 18 18.5 19 19.5 20 20.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 temperature (c) operating current (ma) ber vs. data threshold (32-ddr) (sop threshold = 5, c38 slow) 0.00001 0.0001 0.001 0.01 0.1 1 10 -100 -95 -90 -85 -80 -75 -70 input power (dbm) %ber ber vs. data threshold (32-8dr) (sop threshold = 5, c38 slow) 0.00001 0.0001 0.001 0.01 0.1 1 10 -100 -95 -90 -85 -80 -75 -70 input power (dbm) %ber 0 1 3 6 0 thru 7 gfsk icc rx (lna off) 17 17.5 18 18.5 19 19.5 20 20.5 21 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 temperature (c) operating current (ma) icc rx (lna on) 19 19.5 20 20.5 21 21.5 22 22.5 23 23.5 24 24.5 25 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 temperature (c) operating current (ma) 3.3 v 3.0 v 2.7 v 2.4 v 3.3 v 3.0 v 2.7 v 2.4 v 3.3 v 3.0 v 2.7 v 2.4 v 3.3 v 3.0 v 2.7 v 2.4 v 3.3 v 3.0 v 2.7 v 2.4 v 3.3 v 3.0 v 2.7 v 2.4 v 3.3 v 3.0 v 2.7 v 2.4 v 3.3 v 3.0 v 2.7 v 2.4 v 3.3 v 3.0 v 2.7 v 2.4 v [+] feedback
cyrf6936 document #: 38-16015 rev. *j page 21 of 28 typical operating characteristics (continued) figure 11. ac test loads and waveforms for digital pins icc tx @ pa5 19.5 20 20.5 21 21.5 22 22.5 23 23.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 temperature (c) operating current (ma) icc tx @ pa6 24.5 25 25.5 26 26.5 27 27.5 28 28.5 29 29.5 30 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 temperature (c) operating current (ma) icc tx @ pa7 32.5 33 33.5 34 34.5 35 35.5 36 36.5 37 37.5 38 38.5 39 39.5 40 40.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 temperature (c) operating current (ma) 3.3 v 3.0 v 2.7 v 2.4 v 3.3 v 3.0 v 2.7 v 2.4 v 3.3 v 3.0 v 2.7 v 2.4 v 90% 10% v cc gnd 90% 10% all input pulses output 30 pf including jig and scope output r th equivalent to: v th thvenin equivalent rise time: 1 v/ns fall time: 1 v/ns output 5 pf including jig and scope max typical parameter unit r1 1071 r2 937 r th 500 v th 1.4 v v cc 3.00 v v cc output r1 r2 ac test loads dc test load [+] feedback
cyrf6936 document #: 38-16015 rev. *j page 22 of 28 ordering code definitions ordering information part number radio package name package type operating range CYRF6936-40LFXC transceiver 40-pin qfn 40-pin quad flat package pb-free commercial cyrf6936-40ltxc transceiver 40-pin qfn 40-pin qfn (sawn type) commercial cy marketing code: rf = wireless (radio frequency) product line rf company id: cy = cypress part number 6936 40-pin package f = qfn; t = sawn qfn x = pb-free 40l(f,t)x temperature range: commercial c [+] feedback
cyrf6936 document #: 38-16015 rev. *j page 23 of 28 package description figure 12. 40-pin pb-free qfn 6 6 mm the recommended dimension of the pcb pad size for the e-pad underneath the qfn is 3.5 mm 3.5 mm (width length). pad exposed solderable 001-12917 *c [+] feedback
cyrf6936 document #: 38-16015 rev. *j page 24 of 28 figure 13. 40-pin sawn qfn (6 6 0.90 mm) 001-44328 *d [+] feedback
cyrf6936 document #: 38-16015 rev. *j page 25 of 28 acronyms document conventions units of measure table 9. acronyms used in this document acronym description ack acknowledge (packet received, no errors) ber bit error rate bom bill of materials cmos complementary metal oxide semiconductor crc cyclic redundancy check gfsk gaussian frequency-shift keying hbm human body model ism industrial, scientific, and medical irq interrupt request mcu microcontroller unit qfn quad flat no-leads rssi received signal strength indication rf radio frequency rx receive tx transmit table 10. units of measure symbol unit of measure c degree celsius db decibels dbc decibel relative to carrier dbm decibel-milliwatt hz hertz kb 1024 bytes kbit 1024 bits khz kilohertz k kilohm mhz megahertz m megaohm a microampere s microsecond v microvolts vrms microvolts root-mean-square w microwatts ma milliampere ms millisecond mv millivolts na nanoampere ns nanosecond nv nanovolts ohm pp peak-to-peak ppm parts per million ps picosecond v volts [+] feedback
cyrf6936 document #: 38-16015 rev. *j page 26 of 28 document history page description title: cyrf6936 wirelessusb? lp 2.4 ghz radio soc document number: 38-16015 revision ecn orig. of change submission date description of change ** 307437 tge see ecn new data sheet *a 377574 tge see ecn preliminary release? - updated section 1.0 - features - updated section 2.0 - applications - added section 3.0 - applications support - updated section 4.0 - functional descriptions - updated section 5.0 - pin description - added figure 5-1 - updated section 6.0 - functional overview - added section 7.0 - functional block overview - added section 9.0 - register descriptions - updated section 10.0 - absolute maximum ratings - updated section 11.0 - operating conditions - updated section 12.0 - dc characteristics - updated section 13.0 - ac characteristics - updated section 14.0 - rf characteristics - added section 16.0 - ordering information *b 398756 tge see ecn es-10 update- - changed part no. - updated section 9.0 - register descriptions - updated section 12.0 - dc characteristics - updated section 14.0 - rf characteristics *c 412778 tge see ecn es-10 update- - updated section 4.0 - functional descriptions - updated section 5.0 - pin descriptions - updated section 6.0 - functional overview - updated section 7.0 - functional block overview - updated section 9.0 - register descriptions - updated section 10.0 - absolute maximum ratings - updated section 11.0 - operating conditions - updated section 14.0 - rf characteristics *d 435578 tge see ecn - updated section 1.0 - features - updated section 5.0 - pin descriptions - updated section 6.0 - functional overview - updated section 7.0 - functional block overview - updated section 9.0 - register descriptions - added section 10.0 - recommended radio circuit schematic - updated section 11.0 - absolute maximum ratings - updated section 12.0 - operating conditions - updated section 13.0 - dc characteristics - updated section 14.0 - ac characteristics - updated section 15.0 - rf characteristics *e 460458 boo see ecn final data sheet - removed ?preliminary? notation *f 487261 tge see ecn - updated section 1.0 - features - updated section 5.0 - pin descriptions - updated section 6.0 - functional overview - updated section 7.0 - functional block overview - updated section 8.0 - application example - updated section 9.0 - register descriptions - updated section 12.0 - dc characteristics - updated section 13.0 - ac characteristics - updated section 14.0 - rf characteristics - added section 15.0 - typical operating characteristics [+] feedback
cyrf6936 document #: 38-16015 rev. *j page 27 of 28 *g 778236 oyr/ari see ecn -modified radio function register descriptions -changed l/d pin description -footnotes added -changed rst capacitor from 0.1uf to 0.47 uf -updated figure 9, recommended circuit for systems -updated table 3, recommended bi ll of materials for systems -updated package diagram from ** to *a *h 2640987 vny/oyr/tge/ aesa 02/20/2009 -removed range values in features description -bit level register details removed and appended to the wireless lp and proc trm -updated register summary table 4 -updated pin description diagram (figure 1) -updated the schematic of the radio (figure 10). -removed backward compatibility section. -removed table 2 -updated rf table characteristics for payload size -added pkg diagram 001-12917 -updated bom table 4 on page 10 . -updated table 8 on page 17 with receiver information (t = 25c, v cc = v bat = 3.0 v, f osc = 12.000000 mhz, ber < 1e-3) *i 2673333 tge/pyrs 03/13/2009 corrected figure 9 on page 12 updated packaging and ordering information for 40 qfn (sawn) package *j 3232571 jcjc 04/18/2011 added section receive spurious response on page 9 . added note # 20 and referred in table 8 on page 17 . updated template as per new cypress standards. added ordering code definitions, acronyms, and units of measure. updated package diagrams: 001-12917: *a to *c 001-44328: *c to *d document history page (continued) description title: cyrf6936 wirelessusb? lp 2.4 ghz radio soc document number: 38-16015 revision ecn orig. of change submission date description of change [+] feedback
document #: 38-16015 rev. *j revised april 18, 2011 page 28 of 28 all products and company names mentioned in this document may be the trademarks of their respective holders. cyrf6936 ? cypress semiconductor corporation, 2005-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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